Technologies for Estimating Remaining Life of Integrated Circuits Using On-Chip Memory

A processor-implemented method for estimating a remaining lifetime of an electronic integrated circuit where the electronic integrated circuit includes one or more circuit blocks comprising redundant circuitry, the method comprising:

• detecting a fault in one of the one or more circuit blocks comprising redundant circuitry,
• classifying the fault into one or more wearout mechanisms,
• generating, based on the classification of the fault, a statistical model of time to failure of the one or more circuit blocks comprising redundant circuitry containing the fault,
• generating, based on the statistical model of time to failure of the one or more circuit blocks comprising redundant circuitry containing the fault, a statistical model of time to failure of the electronic integrated circuit;
• and
• estimating, based on the statistical model of time to failure of the electronic integrated circuit, the remaining lifetime of the electronic integrated circuit.

An electronic system in communication with a memory, wherein an electronic integrated circuit is comprised at least in part of the memory, the electronic system comprising:

• a controller;
• a test pattern generator;
• and
• an output response analyzer,
• wherein the electronic system is configured to estimate a remaining lifetime of the electronic integrated circuit by:
• performing a diagnostic on a fault in the memory,
• generating, based on the performed diagnostic, a statistical model of time to failure of the memory,
• generating, based on the statistical model of time to failure of the memory, a statistical model of time to failure of the electronic integrated circuit;
• and
• estimating, based on the statistical model of time to failure of the electronic integrated circuit, the remaining lifetime of the electronic integrated circuit.

A method for updating a physical model of a wearout mechanism, the method comprising:

• detecting a fault in a circuit block containing redundant circuitry,
• providing one or more electrical signals to the circuit block containing redundant circuitry containing the fault,
• monitoring one or more electrical test points within the circuit block containing redundant circuitry containing the fault, wherein the one or more electrical test points provide an output in response to the providing of the one or more electrical signals,
• classifying, based on the monitoring of the one or more electrical test points proving the output, the fault into one of a plurality of wearout mechanisms,
• recording the wearout mechanism in which the fault was classified and a time to failure of the fault, and
• transmitting the recorded wearout mechanism and the time to failure of the fault wherein the transmitted wearout mechanism and the time to failure of the fault is used to update the physical model of the wearout mechanism in which the fault is classified.