Operation of a multi-slice processor implementing dynamic switching of instruction issuance order

A multi-slice processor comprising:

• a plurality of execution slices, wherein the multi-slice processor is configured to carry out the steps of:
• determining a current issuance order for a plurality of instructions and a change in an operating condition of the multi-slice processor;
• responsive to determining the change in the operating condition, determining an alternate issuance order for the plurality of instructions;
• and
• responsive to determining the alternate issuance order, switching from the current issuance order for the plurality of instructions to the alternate issuance order for the plurality of instructions.

An apparatus comprising:

• a plurality of execution slices, wherein the multi-slice processor is configured to carry out the steps of:
• determining a current issuance order for a plurality of instructions and a change in an operating condition of the multi-slice processor;
• responsive to determining the change in the operating condition, determining an alternate issuance order for the plurality of instructions;
• and
• responsive to determining the alternate issuance order, switching from the current issuance order for the plurality of instructions to the alternate issuance order for the plurality of instructions.