Adaptive mechanism for synchronized or asynchronized memory devices

A storage node comprising:

• a hybrid memory group comprising:
• a non-volatile memory device;
• and
• a volatile memory device coupled to the non-volatile memory device;
• and
• a hybrid memory controller configured to perform data transfer to/from the volatile and non-volatile memory devices through a same channel, the hybrid memory controller comprising:
• a processor;
• and
• a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to perform:
• identifying the volatile and non-volatile memory devices by detecting an associated serial presence detect (SPD) data stored in each of the volatile and non-volatile memory devices;
• receiving a first central processing unit (CPU) request to write to/read from the hybrid memory group;
• identifying the volatile memory device as a first target of the first CPU request by decoding and address mapping of the first CPU request;
• queuing the first CPU request in a first buffer;
• receiving a second CPU request to write to/read from the hybrid memory group;
• identifying the non-volatile memory device as a second target of the second CPU request by decoding and address mapping of the second CPU request;
• queuing the second CPU request in a second buffer;
• determining an arbitration policy based on the SPD data associated with the volatile and non-volatile memory devices;
• generating, based on the arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and, in response, generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets;
• and
• transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

A method of controlling a hybrid memory group comprising a volatile memory device and a non-volatile memory device, the method comprising:

• receiving, by a processor, a first central processing unit (CPU) request to write to/read from the hybrid memory group;
• identifying, by the processor, the volatile memory device as a first target of the first CPU request by decoding and address mapping of the first CPU request;
• queuing, by the processor, the first CPU request in a first buffer;
• receiving, by the processor, a second CPU request to write to/read from the hybrid memory group;
• identifying, by the processor, the non-volatile memory device as a second target of the second CPU request by decoding and address mapping of the second CPU request;
• queuing, by the processor, the second CPU request in a second buffer;
• generating, by the processor, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and, in response, generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets;
• and
• transmitting, by the processor, the first and second commands to respective ones of the volatile and non-volatile memory devices.

A hybrid memory controller for controlling a hybrid memory group comprising a volatile memory device and a non-volatile memory device, the hybrid memory controller comprising:

• an address mapper/decoder configured to receive a first central processing unit (CPU) request and a second CPU request to write to/read from the hybrid memory group, to identify the volatile memory device as a first target of the first CPU request by decoding and address mapping of the first CPU request, and to identify the non-volatile memory device as a second target of the second CPU request by decoding and address mapping of the second CPU request;
• a first transaction queue configured to queue the received first CPU request;
• a second transaction queue configured to queue the received second CPU request;
• an arbitrator configured to determine an arbitration policy based on SPD data associated with the volatile and non-volatile memory devices;
• and
• a scheduler configured to generate, based on the arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and to generate a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and to transmits the first and second commands to respective ones of the volatile and non-volatile memory devices.