Dram controller with adaptive precharge policy
AssigneeMarvell World Trade Ltd.
InventorsMichael Weiner, Hunglin Hsu, Nadav Klein, Junhua Xu, Chia-Hung Chien
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AssigneeMarvell World Trade Ltd.
InventorsMichael Weiner, Hunglin Hsu, Nadav Klein, Junhua Xu, Chia-Hung Chien
Estimating the term…
A Dynamic Random Access Memory (DRAM) controller includes a memory interface and a processor. The memory interface is configured to communicate with a DRAM including one or more memory banks. The processor is configured to receive Input/Output (I/O) commands, each I/O command addressing a respective memory bank and a respective row within the memory bank to be accessed in the DRAM, to further receive one or more indications, indicative of likelihoods that a subsequent I/O command will address a same row in a same memory bank as a previous I/O command, to adaptively set, based on the indications, a policy of deactivating rows of the DRAM, and to execute the I/O commands in the DRAM in accordance with the policy.
A Dynamic Random Access Memory (DRAM) controller, comprising:
A method for controlling a Dynamic Random Access Memory (DRAM) comprising one or more memory banks, the method comprising:
A system, comprising:
Dependencies are inferred from the claim text.