Power saving techniques for memory systems

A memory system comprising:

• an input/output (JO) block configured to be coupled to a memory bus;
• a memory bank comprising memory elements, the memory bank communicatively coupled to the JO block;
• and
• a write register operative to receive data from the memory bus through the JO block and duplicate the data a number of times according to a command from a host processor.

A host processor comprising:

• a physical layer (PHY) interface configured to be coupled to a plurality of data lanes of a memory bus;
• a read register;
• and
• a memory controller coupled to the PHY interface, wherein the memory controller is configured to:
• receive data through the PHY interface from a memory system;
• and
• cause data within the read register to be duplicated based on information received from the memory system.

An apparatus comprising:

• a host processor comprising a memory controller and a physical layer (PHY) interface;
• a memory system;
• and
• a memory bus, wherein the host processor sends data to be written into the memory system via the PHY interface and the memory bus, and
• wherein the memory controller comprises a data pattern checker logic circuit, and is operative to:
• use the data pattern checker logic circuit to determine if patterns of repeatable data exist in the data to be written to into the memory system over the memory bus;
• and
• consolidate the data to reduce data sent over the memory bus.

An apparatus comprising:

• a host processor comprising a memory controller and a physical layer (PHY) interface;
• a memory system;
• and
• a memory bus, wherein the host processor receives data read from the memory system via the PHY interface and the memory bus, and
• wherein the memory system is operative to determine if patterns of repeatable data exist in the data being read from the memory system and consolidate the data to reduce data sent over the memory bus in response to a read command from the host processor.