Magnetic random access memory with dynamic random access memory (dram)-like interface

A memory device configured to emulate dynamic random access memory (DRAM) comprising:

• a memory array including a plurality of memory cells organized into rows and columns, at least one row of memory cells comprising one or more pages that store data during a burst write operation, said data including sequential data units that are written to a page;
• a control circuit operable to:
• initiate said burst write operation that writes said data to said memory array, said burst write operation spanning multiple clock cycles;
• and
• after receiving one or more data units of said data by said memory array, allow a subsequent burst write or read command to begin before completion of said burst write operation in progress;
• an encoder operable to encode said data to be written to said memory array;
• and
• a decoder coupled to said memory array and operable to check and correct said data previously encoded by said encoder and saved in said memory array.