Polysynchronous stochastic circuits
AssigneeRegents of the University of Minnesota
InventorsDavid J. Lilja, Mohammadhassan Najafi, Marcus Riedel, Kiarash Bazargan
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Abstract
In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.
Claims24
A device comprising:
- an integrated circuit including two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks,
- wherein each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one, and
- wherein the respective input clocks are unsynchronized.
A method of operating an integrated circuit, wherein the integrated circuit comprises two or more computational units, the method comprising:
- receiving, at each of the two or more computational units, respective stochastic bit streams;
- receiving, at each of the two or more computational units, clock signals from respective input clocks;
- and
- processing, at each of the two or more computational units, the respective stochastic bit streams in accordance with the respective input clocks,
- wherein each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one, and
- wherein the respective input clocks for each of the two or more computational units are unsynchronized.
An integrated circuit comprising:
- two or more computational units configured to process respective stochastic bit streams in accordance with a global clock signal received from a clock distribution network, wherein each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one;
- and
- a clock distribution circuit to generate the global clock signal without having timing elements to substantially synchronize arrival of global clock signal at the computation units.
Dependencies are inferred from the claim text.