Ultra-Fast Autonomous Clock Monitoring Circuit for Safe and Secure Automotive Applications

A method of monitoring a clock with a circuit monitoring component, comprising:

• configuring the clock to be monitored;
• configuring plurality of delay elements in the circuit monitoring component;
• clearing a plurality of flops in the circuit monitoring component;
• passing a clock pulse from the clock through the plurality of delay elements and the plurality of flops and waiting until the plurality of flops in the circuit monitoring component are loaded;
• encoding loaded flop values to generate an encoded value;
• determining whether the encoded value matches a programmed value;
• and
• generating an interrupt in response to determining that the encoded value matches does not match the programmed value.

A clock monitoring circuit, comprising:

• a plurality of flops;
• a plurality of delay elements, each of which is coupled to one of the plurality of flops;
• means for configuring a clock to be monitored;
• means for configuring the plurality of delay elements;
• means for clearing the plurality of flops;
• means for passing a clock pulse from the clock through the plurality of delay elements and the plurality of flops and waiting until the plurality of flops are loaded;
• means for encoding loaded flop values to generate an encoded value;
• means for determining whether the encoded value matches a programmed value;
• and
• means for generating an interrupt in response to determining that the encoded value matches does not match the programmed value.

A system on chip, comprising:

• a clock to be monitored;
• and
• a clock monitoring circuit coupled to the clock to be monitored, wherein the clock monitoring circuit comprises:
• a plurality of cascaded flops in which a clock input of each flop is the same as the clock to be monitored, a data input of each flop is driven by a divided version of the clock being monitored so that a data input to each of the plurality of cascaded flops is delayed relative to other cascaded flops via one or more programmable delay elements;
• an encoder coupled to outputs of the cascaded flops and configured to generate an encoded output value that represents the outputs of the cascaded flops;
• a comparator configured to generate and store an interrupt when the encoded output value does not match a programmed value;
• and
• an error correction code generator configured to generate and store an error correction code for each stored interrupt.