Tft substrates and the manufacturing methods thereof

A manufacturing method of TFT array substrates, comprising:

• providing a substrate;
• forming a first metallic layer on the substrate, and etching the first metallic layer by a first masking process to be a bottom gate electrode;
• forming a first metal oxide semiconductor layer on the substrate, and adopting a second masking process to etch the first metal oxide semiconductor layer to be a first semiconductor pattern and a second semiconductor pattern, applying a doping process to process the first semiconductor pattern to be a first conductor pattern and second conductor pattern and to process the second semiconductor pattern to be a third conductor pattern, the first conductor pattern and the second conductor pattern are spaced apart from each other, wherein remaining first semiconductor pattern is above the bottom gate electrode, and the third conductor pattern operates as a common electrode;
• wherein photoresist patterns are formed on the metal oxide semiconductor layer, the photoresist patterns comprises a first photoresist pattern corresponding to the first semiconductor pattern and a second photoresist pattern corresponding to the second metal oxide semiconductor layer, a thickness of a middle area of the first photoresist patterns is larger than the thickness of two ends of the first photoresist patterns and is larger than the thickness of the second photoresist patterns;
• the first photoresist patterns and the second photoresist patterns are adopted as masks to etch the metal oxide semiconductor layer to be a first semiconductor pattern and a second semiconductor pattern;
• adopting a plasma treatment toward the first semiconductor pattern and the second semiconductor pattern with the mask of the first photoresist patterns and the second photoresist patterns, processing the two ends of the first semiconductor pattern to be the first conductor pattern and the second conductor pattern, and processing the second semiconductor pattern to be the third conductor pattern;
• forming an etch blocking layer on the substrate, and adopting a sixth masking process to etch the etch blocking layer to form through holes on the etch blocking layer respectively above the first conductor pattern and the second conductor pattern;
• forming a second metallic layer on the substrate, and adopting a third masking process to etch the second metallic layer to be a source electrode and a drain electrode, wherein the drain electrode covers the first semiconductor pattern, and the source electrode covers the second semiconductor pattern;
• forming a passivation layer on the substrate, and adopting a fourth masking process to etch the passivation layer to form a through hole;
• forming a second metal oxide semiconductor layer on the substrate, and adopting a fifth masking process to etch the second metal oxide semiconductor layer to form a top gate electrode and the pixel electrode, wherein the top gate electrode is above the remaining first semiconductor pattern, and at least a portion of the pixel electrode is overlapped with the common electrode, and one of the pixel electrodes electrically connects to the source electrode or the drain electrode via the through hole.