Core Independent Ultrasonic Proximity Sensing Peripheral

An ultrasonic proximity sensing device, comprising:

• a microcontroller comprising
• a central processor and memory, and
• a plurality of core independent peripherals (CIPs) comprising
• an analog-to-digital converter (ADC),
• a configurable logic cell (CLC),
• a data signal modulator (DSM),
• a hardware limit timer (HLT),
• a fixed voltage reference (FVR),
• an operational amplifier (OPA),
• a programmable ramp generator (PRG),
• a pulse width modulation generator (PWM), and
• a timer counter register (TMR);
• an ultrasonic transmitting transducer coupled to the DSM;
• and
• an ultrasonic receiving transducer coupled to a receive OPA;
• wherein the selected CIPs are configured to
• generate signals to be transmitted as ultrasonic pulses from the ultrasonic transmitting transducer,
• receive signals representing reflected ultrasonic pulses with the ultrasonic receiving transducer,
• detect the received signals,
• integrate the detected signals to voltage value,
• sample the voltage value,
• store the sampled voltage value as a present voltage value,
• compare the present voltage value to a prior stored voltage value average, and
• generate a proximity sensed signal when the present voltage value is different than the prior stored voltage value average.

A microcontroller, comprising

• a central processing unit and memory;
• and
• configurable logic cell modules configured to provide first and second RS-flip flops,
• a first and second timer,
• a data signal modulator (DSM),
• an analog-to-digital converter (ADC),
• a first operational amplifier,
• a voltage reference module, and
• a pulse width modulation (PWM) unit;
• wherein the microcontroller is configured such that a PWM signal is fed to the DSM which generates an output PWM signal fed to an external pin and a clock input of the first timer whose output is fed to a reset input of the first SR-flip flop which receives a start signal at its set input and provides an output signal which is fed back to the DSM;
• wherein the start signal is further fed to a reset input of the second SR-flip-flop whose output triggers the second timer controlling the ADC;
• and
• wherein the first operational amplifier is configured as an integrator receiving an output signal from the ultrasonic receiver and a voltage reference from the voltage reference module.