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US 2017/0254848 A1Published application
Circuit and method for detecting a fault attack
AssigneeSTMicroelectronics (Rousset) SAS
InventorFrancesco La Rosa
Life of this patent
Estimating the term…
Abstract
A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of the interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.
Claims18
A static volatile memory cell, comprising:
- first, second, and third MOS transistors connected between first and second power supply terminals, the second and third MOS transistors having gates connected together;
- fourth, fifth, and sixth MOS transistors connected between the first and second power supply terminals, the fifth and sixth MOS transistors having gates connected together and to a first node between the second and third MOS transistors, and the gates of the second and third MOS transistors being connected to a second node between the fifth and sixth MOS transistors;
- a first capacitor connected between a gate of the first MOS transistor and said second power supply terminal;
- a second capacitor connected between a gate of the fourth MOS transistor and said second power supply terminal;
- and
- a seventh MOS transistor having a source, drain, and bulk connected to the gates of the second and third MOS transistors and having a gate connected to the gate of the first MOS transistor.
3 more elements
A static volatile memory cell, comprising:
- first and second transistors electrically coupled between first and second power supply terminals, the first and second transistors having control terminals connected together;
- third and fourth transistors electrically coupled between the first and second power supply terminals, the third and fourth MOS transistors having control terminals connected together and to a first node between the first and second transistors, and the control terminals of the first and second transistors being connected to a second node between the third and fourth transistors;
- a fifth transistor having a source, drain, and bulk connected to the control terminals of the first and second transistors and to the second node;
- and
- a first capacitor connected between a gate of the fifth transistor and the second power supply terminal.
2 more elements
A counter, comprising:
- a plurality of static volatile memory cells configured to store count values, each static volatile memory cell including:
- first and second transistors electrically coupled between first and second power supply terminals, the first and second transistors having control terminals connected together;
- third and fourth transistors electrically coupled between the first and second power supply terminals, the third and fourth MOS transistors having control terminals connected together and to a first node between the first and second transistors, and the control terminals of the first and second transistors being connected to a second node between the third and fourth transistors;
- a fifth transistor having a source, drain, and bulk connected to the control terminals of the first and second transistors and to the second node;
- and
- a first capacitor connected between a gate of the fifth transistor and the second power supply terminal.
3 more elements
A chip card, comprising:
- a counter that includes:
- a plurality of static volatile memory cells configured to store count values, each static volatile memory cell including:
- first and second transistors electrically coupled between first and second power supply terminals, the first and second transistors having control terminals connected together;
- third and fourth transistors electrically coupled between the first and second power supply terminals, the third and fourth MOS transistors having control terminals connected together and to a first node between the first and second transistors, and the control terminals of the first and second transistors being connected to a second node between the third and fourth transistors;
- a fifth transistor having a source, drain, and bulk connected to the control terminals of the first and second transistors and to the second node;
- and
- a first capacitor connected between a gate of the fifth transistor and the second power supply terminal.
4 more elements
Dependencies are inferred from the claim text.