On-chip leakage measurement

An apparatus for measuring semiconductor device leakage comprising:

• a semiconductor device powered by a supply voltage and having at least one circuit block comprising a plurality of transistors;
• a system clock on the semiconductor device;
• a test circuit provided on the semiconductor device to measure semiconductor device leakage;
• a power supply to provide a fixed voltage to the test circuit to power the test circuit;
• the test circuit comprising a voltage monitor to output a first value indicative of a first voltage, Vhigh and a second value indicative of second voltage, Vlow wherein Vhigh is greater than Vlow;
• a fixed-frequency measurement clock separate from the system clock;
• a counter for providing a semiconductor device leakage metric and receiving an input from the fixed-frequency measurement clock and receiving an input from the test circuit;
• responsive to the voltage monitor outputting the first value, the counter starts counting;
• responsive to the voltage monitor outputting the second value, the counter stops counting.

A computer program product for measuring semiconductor device leakage on a semiconductor device powered by a supply voltage and having at least one circuit block comprising a plurality of transistors and providing on the semiconductor device a test circuit, a fixed-frequency measurement clock and a counter for providing a semiconductor device leakage metric such that the test circuit and fixed-frequency measurement clock both providing an input to the counter, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computing device to cause the device to perform a method comprising:

• disconnecting a system clock from the circuit block, wherein the system clock, in the absence of the disconnecting, causes the circuit block to switch from a first state to a second state;
• receiving by the test circuit the supply voltage as an input;
• initializing the counter;
• starting the counter when the supply voltage is at or below a first voltage Vhigh;
• monitoring a decrease of the supply voltage with time;
• stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow;
• and
• reading the counter to provide the semiconductor device leakage metric.