US 2017/0254844 A1 · Impedance Analyzer Using Square Wave Stimuli

Abstract

A microcontroller-based system for measuring the impedance of a device under test (DUT) (35) responsive to a square wave stimulus. A clock generator circuit (26) in the microcontroller (20) generates a clock signal at a base clock frequency. A first timer (25) divides down the base clock frequency by a first frequency divisor integer to set the stimulus frequency of a square wave generated by a general purpose input/output (GPIO) function (24), and a second timer (28) divides down the base clock frequency by a second frequency divisor integer to set the sampling frequency of an analog-to-digital converter (ADC) (30). A discrete Fourier transform executed by a processor (22) is used to determine the impedance of the DUT at the stimulus frequency. The first and second integers are selected so that aliased harmonics fall in different DFT bins from the fundamental tone.

Claims19

Dependent claims

A circuit for measuring an impedance of a device under test (DUT), comprising:

clock circuitry generating a base clock signal;
a driver circuit for generating a square wave stimulus at stimulus frequency having a period corresponding to a first integer number of cycles of the base clock signal;
an anti-aliasing filter coupled to the DUT, for filtering the stimulus to remove high frequencies;
an amplifier circuit coupled to the DUT to present a response signal from the DUT in response to the filtered stimulus;
an analog-to-digital converter (ADC) for sampling the response signal at a sample frequency having a period corresponding to a second integer number of cycles of the base clock signal;
and
processor circuitry coupled to the ADC, programmed to execute a discrete Fourier transform on the sampled response signal, using a window of samples numbering an integer multiple of a separation number defined by the first integer divided by the greatest common divisor of the first and second integers.

4 more elements

A method of measuring an impedance of a device under test (DUT), comprising:

generating a base clock signal at a base clock frequency;
selecting a first target frequency of a stimulus signal;
selecting a first frequency divisor integer so that the base clock frequency divided by the first frequency divisor integer is near the first target frequency;
selecting a second frequency divisor integer;
applying, to the DUT, a square wave stimulus signal at a stimulus frequency corresponding to the base clock frequency divided by the first frequency divisor integer;
sampling a response signal corresponding to the response of the DUT to the square wave stimulus signal, at a sampling frequency corresponding to the base clock frequency divided by the second frequency divisor integer, to produce a sample stream;
computing a discrete Fourier transform (DFT) on a DFT window having a number of samples that is an integer multiple of a separation number defined as the first frequency divisor integer divided by the greatest common divisor of the first and second frequency divisor integers;
and
determining the impedance of the DUT from a magnitude and phase results of the DFT at a selected bin corresponding to the stimulus frequency.

6 more elements

Dependencies are inferred from the claim text.

Impedance Analyzer Using Square Wave Stimuli

Life of this patent

Impedance Analyzer Using Square Wave Stimuli

Life of this patent

Abstract

Claims19