Circuit and Method of a Level Shift Network with Increased Flexibility

Abstract

A circuit and method for a level shift circuit with increased flexibility is described. The level shifting circuit includes an NMOS pair, a PMOS pair cross-coupled to the NMOS pair, an auxiliary transient response network parallel to the PMOS pair configured to provide a parallel current path, and a delay network configured to provide a delay to the auxiliary transient response network. Additionally, a method of providing a level shift circuit includes the steps of (a) providing an NMOS pair, (b) cross-coupling the NMOS pair to a PMOS pair, connected in parallel with an auxiliary transient response network which includes a pair of cascode PMOS, and a step (c) of providing a pair of delay inverters at inputs to the auxiliary transient response network.

Dependencies are inferred from the claim text.