Method of manufacturing three-dimensional semiconductor device

Abstract

A method of manufacturing three-dimensional semiconductor device, comprising the steps of: forming a stack structure of a plurality of a first material layers and a second material layers on a substrate in the memory cell region; etching said stack structure to form a plurality of trenches; forming channel layers in said plurality of trenches; performing annealing treatment to at least one surface of the channel layers to reduce the surface roughness and the interface state. In accordance with the three-dimensional semiconductor device manufacturing method of the present invention, the formation of interface states is depressed by introducing a dummy channel sacrificial layer for the interface treatment on the channel surface and back surface, and/or the channel surface roughness is reduced by introducing a buffer layer on the channel surface and back surface during the treatment, which can improve the channel carrier mobility, improve the channel current as well as the reliability of the memory cell.

Dependencies are inferred from the claim text.