US 2017/0250190 A1Published application

Memory array having connections going through control gates

AssigneeMicron Technology, Inc.

InventorsToru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda

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Abstract

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

Claims16

Dependent claims

An apparatus comprising:

a first memory array including a first memory cell string over a substrate, and a first select gate and control gates located along a body of the first memory string and over the substrate;
a second memory array including a second memory cell string over the substrate, and a second select gate and control gates located along a body of the second memory string and over the substrate;
a first connection coupled to the first select gate and including a portion going through a portion of a first control gate among the control gates of the first memory array;
a second connection coupled to the second select gate and including a portion going through a portion of a second control gate among the control gates of the second memory array;
and
a third connection coupling the first connection to the second connection.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/457,473Filed 13 Mar 2017
Priority: 30 Aug 2012
Published: 31 Aug 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/41
Characterised by the peripheral circuit region: of a memory region comprising a cell select transistor, e.g. NAND

Family

Application13/599,793Division · filed 30 Aug 2012
Application15/457,473Division
US 10,770,470 B2Related patent
US 2014/0061747 A1Published application
US 9,595,533 B2Related patent
US 2017/0250190 A1This patent

From the US filing history. Foreign family members aren’t listed.

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