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US 2017/0249893 A1Published application
Gate driver and display apparatus including the same
AssigneeSamsung Display Co., Ltd.
InventorsCHOLHO KIM, GUNWOO YANG, HYUNYOUNG CHOI, JIHOON YANG, YONGWOO LEE
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Abstract
A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.
Claims18
A gate driver comprising:
- a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration;
- and
- a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down circuit in the second duration in response to a second clock signal.
A gate driver comprising:
- a pull-up circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration;
- a pull-down circuit configured to pull down the gate signal to a first off voltage in a second duration in response to a next carry signal output by a next stage;
- an inverting circuit configured to generate a current inverting signal based on the first clock signal and a second off voltage;
- and
- a pull-down boosting circuit configured to output the second off voltage to the pull-up circuit in the second duration in response to a previous inverting signal output by a previous stage.
2 more elements
A display apparatus comprising:
- a data driver configured to generate a data voltage based on input image data;
- a gate driver comprising:
- a first transistor connected between a first clock terminal and a gate output terminal and comprising a first control electrode connected to a first node;
- a fourth transistor connected between a previous carry terminal and the first node and comprising a fourth control electrode connected to the previous carry terminal;
- a ninth transistor connected between the first node and a first off terminal and comprising a ninth control electrode connected to a next carry terminal;
- a tenth transistor connected between the first node and the first off terminal and comprising a tenth control electrode connected to the first node;
- and
- an eighteenth transistor connected between the first clock terminal and the first off terminal and comprising an eighteenth control electrode connected to an inversion terminal;
- and
- a display panel configured to display an image based on the data voltage and the gate signal,
- wherein a first clock signal is configured to be applied to the first clock terminal, a gate signal is configured to be output to the gate output terminal, a first off voltage is configured to be applied to the first off terminal, a previous carry signal is configured to be applied to the previous carry terminal, a next carry signal is configured to be applied to the next carry terminal, and an inversion signal is configured to be applied to the inversion terminal,
- wherein the inversion signal has a low level during the first clock signal has a high level.
9 more elements
Dependencies are inferred from the claim text.