Inter-bus communication interface device

A security network controller comprising:

• a main bus;
• a central processing unit (CPU) coupled to the main bus;
• a cryptographic processing circuit coupled to the main bus;
• a security control circuit coupled to the main bus;
• a first dedicated bus coupled between the cryptographic processing circuit and the security control circuit;
• a memory controller coupled to the main bus and memory, wherein the security control circuit is configured to:
• receive data stored in memory from the memory controller;
• send the data over the first dedicated bus to the cryptographic processing circuit to obtain encrypted data;
• receive the encrypted data over the first dedicated bus from the cryptographic processing circuit;
• and
• send the encrypted data to the memory controller, the memory controller to store the encrypted data in the memory.

A method of operating a security network controller, the method comprising:

• receiving, at a security control circuit, data stored in memory from a memory controller;
• sending, by the security control circuit, the data over a first dedicated bus to a cryptographic processing circuit to obtain encrypted data;
• encrypting, by the cryptographic processing circuit, the data to obtain encrypted data;
• receiving, by the security control circuit, the encrypted data over the first dedicated bus from the cryptographic processing circuit;
• transferring, by the security control circuit, the encrypted data to the memory controller;
• and
• storing, by the memory controller, the encrypted data in the memory.

A system comprising:

• a main central processing unit (CPU);
• a security network controller comprising an external connection interface coupled to the main CPU and a communication interface coupled to a network, wherein the security network controller further comprises:
• a main bus;
• a CPU coupled to the main bus;
• a cryptographic processing circuit coupled to the main bus;
• a security control circuit coupled to the main bus;
• a first dedicated bus coupled between the cryptographic processing circuit and the security control circuit;
• a memory controller coupled to the main bus and memory, wherein the security control circuit is configured to:
• receive data stored in memory from the memory controller;
• send the data over the first dedicated bus to the cryptographic processing circuit to obtain encrypted data;
• receive the encrypted data over the first dedicated bus from the cryptographic processing circuit;
• and
• send the encrypted data to the memory controller, the memory controller to store the encrypted data in the memory.