Channel Strain Inducing Architecture and Doping Technique at Replacement Poly Gate (RPG) Stage

A fin field field-effect transistor (FinFET), comprising:

• a semiconductor fin extending over a semiconductor substrate;
• a first source/drain region and a second source/drain region disposed on or within the semiconductor fin, the first source/drain region being spaced apart from the second source/drain region by a channel region;
• first and second source/drain extension regions being arranged on opposite sides of the channel region, the first source/drain extension region disposed between the first source/drain region and the channel region, and the second source/drain extension region disposed between the channel region and the second source/drain region;
• a metal gate electrode straddling the channel region and being separated from the channel region by a gate dielectric and a strain-inducing layer;
• first and second inner spacers disposed over the first and second source/drain extension regions, respectively, and having inner sidewalls disposed along outer sidewalls of the metal gate electrode;
• and
• first and second outer spacers disposed over the first and second source/drain extension regions, respectively, and having inner sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively.

A fin field-effect transistor (finFET) device comprising:

• a semiconductor fin above a semiconductor substrate;
• a source region and a drain region within the semiconductor fin;
• first and second lightly doped drain (LDD) regions which are arranged within the semiconductor fin and which abut innermost side walls of the source and the drain regions;
• a channel region connecting the first and second LDD regions;
• a strain inducing layer over an upper surface of the channel region;
• one or more pairs of spacers above the first and second LDD regions;
• and
• a replacement gate stack abutting a top surface of the strain inducing layer.