Methods of forming memory arrays

A method of forming a memory array, comprising:

• forming a first dielectric over a semiconductor;
• forming a first conductor over the first dielectric;
• forming a second dielectric over the first conductor;
• forming a cap over the second dielectric;
• forming a first hole passing through the cap, the second dielectric, the first conductor, and the first dielectric, stopping on the semiconductor so that the first hole exposes an edge of the cap, an edge of the second dielectric, an edge of the first conductor, and an edge of the first dielectric and a portion of the semiconductor;
• forming a third dielectric in the first hole and on the exposed edge of the cap, on the exposed edge of the second dielectric, on the exposed edge of the first conductor, and on the exposed edge of the first dielectric so that the third dielectric lines the first hole;
• filling the first hole that is lined with third dielectric with a second conductor;
• forming a fourth dielectric over the cap;
• forming a third conductor over the fourth dielectric;
• forming a fifth dielectric over the third conductor;
• forming a fourth conductor over the fourth dielectric;
• forming a second hole that is circular passing through the fourth conductor, the fifth dielectric, the third conductor, and the fourth dielectric so that the second hole exposes an edge of the fourth conductor, an edge of the fifth dielectric, an edge of the third conductor, and an edge of the fourth dielectric and so that the second hole exposes an upper surface of the second conductor;
• forming a charge trapping layer within the second hole and on the exposed edge of the fourth conductor, on the exposed edge of the fifth dielectric, on the exposed edge of the third conductor, and on the exposed edge of the fourth dielectric so that the charge trapping layer lines the second hole;
• filling the second hole that is lined with the charge trapping layer with a fifth conductor so the fifth conductor is in contact with the second conductor;
• forming a first slot and a second slot passing through the fourth conductor, the fifth dielectric, the third conductor, and the fourth dielectric so that the fifth conductor that fills second hole that is lined with the charge trapping layer is between the first slot and the second slot and so that the first slot cuts through at least a portion of a first portion of the charge trapping layer and the second slot cuts through at least a portion of a second portion of the charge trapping layer;
• and
• filling the first slot with a sixth dielectric to form a first isolation region and the second slot with the sixth dielectric to form a second isolation region.

A method of forming a memory array, comprising:

• forming a first dielectric over a semiconductor;
• forming a first conductor over the first dielectric;
• forming a second dielectric over the first conductor;
• forming a cap over the second dielectric;
• forming a first hole passing through the cap, the second dielectric, the first conductor, and the first dielectric, stopping on the semiconductor so that the first hole exposes an edge of the cap, an edge of the second dielectric, an edge of the first conductor, and an edge of the first dielectric and a portion of the semiconductor;
• forming a third dielectric in the first hole and on the exposed edge of the cap, on the exposed edge of the second dielectric, on the exposed edge of the first conductor, and on the exposed edge of the first dielectric so that the third dielectric lines the first hole;
• filling the first hole that is lined with third dielectric with a second conductor;
• forming a fourth dielectric over the cap;
• forming a third conductor over the fourth dielectric;
• forming a fifth dielectric over the third conductor;
• forming a fourth conductor over the fourth dielectric;
• forming a second hole that is circular passing through the fourth conductor, the fifth dielectric, the third conductor, and the fourth dielectric so that the second hole exposes an edge of the fourth conductor, an edge of the fifth dielectric, an edge of the third conductor, and an edge of the fourth dielectric and so that the second hole exposes an upper surface of the second conductor;
• forming a charge trapping layer within the second hole and on the exposed edge of the fourth conductor, on the exposed edge of the fifth dielectric, on the exposed edge of the third conductor, and on the exposed edge of the fourth dielectric so that the charge trapping layer lines the second hole;
• filling the second hole that is lined with the charge trapping layer with a fifth conductor so the fifth conductor is in contact with the second conductor;
• forming a first slot and a second slot passing through the fourth conductor, the fifth dielectric, the third conductor, and the fourth dielectric so that the fifth conductor that fills second hole that is lined with the charge trapping layer is between the first slot and the second slot and so that the first slot cuts through at least a portion of a first portion of the charge trapping layer and the second slot cuts through at least a portion of a second portion of the charge trapping layer;
• filling the first slot with a sixth dielectric to form a first isolation region and the second slot with the sixth dielectric to form a second isolation region;
• forming a seventh dielectric over the fourth conductor, the first and second isolation regions, and the fifth conductor;
• forming a eighth dielectric over the seventh dielectric;
• forming a ninth dielectric over the eighth dielectric;
• forming a sixth conductor over the ninth dielectric;
• forming a tenth dielectric over the sixth conductor;
• forming an eleventh dielectric over the tenth dielectric;
• forming a twelfth dielectric over the eleventh dielectric;
• forming a third hole passing through the twelfth dielectric, the eleventh dielectric, the tenth dielectric, the sixth conductor, ninth dielectric, the eighth dielectric, and the seventh dielectric, stopping on the fifth conductor, so that the third hole exposes an edge of the twelfth dielectric, an edge of the eleventh dielectric, an edge of the tenth dielectric, an edge of the sixth conductor, an edge of ninth dielectric, an edge of the eighth dielectric, and an edge of the seventh dielectric and an upper surface of the fifth conductor;
• forming a thirteenth dielectric in the third hole and on the exposed edge of the twelfth dielectric, on the exposed edge of the eleventh dielectric, on the exposed edge of the tenth dielectric, on the exposed edge of the sixth conductor, on the exposed edge of ninth dielectric, on the exposed edge of the eighth dielectric, and on the on the exposed edge of the seventh dielectric so that the thirteenth dielectric lines the third hole;
• and
• filling the third hole lined with the thirteenth dielectric with a seventh conductor;
• and
• forming an eighth conductor over an upper surface of the seventh conductor and an upper surface of the twelfth dielectric.