Method for forming a split-gate flash memory cell device with a low power logic device

A method for manufacturing an embedded flash memory device, the method comprising:

• forming a gate stack over a semiconductor substrate, wherein the gate stack includes a floating gate and a control gate arranged over the floating gate;
• forming a gate layer over the gate stacks and the semiconductor substrate, and further lining sidewalls of the gate stacks;
• forming an erase gate from the gate layer, wherein the erase gate is formed adjacent to a first side of the gate stack;
• and
• concurrently forming a word line and a logic gate from the gate layer, wherein the word line is formed adjacent to a second side of the gate stack, opposite the first side.

A method for manufacturing an embedded flash memory device, the method comprising:

• forming a pair of gate stacks spaced over a semiconductor substrate, wherein the gate stacks include floating gates and control gates arranged over the floating gates;
• forming a common gate layer over the gate stacks and the semiconductor substrate, and further lining sidewalls of the gate stacks;
• performing a first etch into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to further form an erase gate between the gate stacks;
• forming hard masks respectively over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer;
• and
• performing a second etch into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate respectively from the word line and logic gate regions of the common gate layer.