High breakdown voltage iii-n depletion mode mos capacitors

A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:

• a (110) silicon substrate having a non-planar silicon body formed therein, the non-planar silicon body having an exposed (111) sidewall;
• a GaN layer disposed on the exposed (111) sidewall of the non-planar silicon body;
• a III-N barrier layer disposed on a (0001) surface of the GaN layer, wherein the (0001) surface of the GaN layer is a sidewall of a non-planar GaN body formed in the GaN layer;
• a dielectric layer disposed over the III-N barrier layer;
• a first contact metal disposed on the dielectric layer;
• and
• a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer.

A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:

• a (001) silicon substrate having a trench formed therein with exposed (111) sidewalls;
• a GaN layer disposed the trench of the (001) silicon substrate;
• a III-N barrier layer disposed on a (0001) surface of the GaN layer;
• a dielectric layer disposed over the III-N barrier layer;
• a first contact metal disposed on the dielectric layer;
• a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer;
• and
• a third contact disposed on a second n-type semiconductor electrically connected to the 2DEG on a side of the first contact opposite the second contact, wherein the second and third contacts are electrically connected as one voltage node of the capacitor.

A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:

• a (001) silicon substrate having a trench formed therein with exposed (111) sidewalls;
• a GaN layer disposed the trench of the (001) silicon substrate;
• a III-N barrier layer disposed on a (0001) surface of the GaN layer;
• a dielectric layer disposed over the III-N barrier layer;
• a first contact metal disposed on the dielectric layer;
• and
• a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer, wherein the capacitor has a breakdown voltage exceeding 4V across the first and second contacts.

A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:

• a (110) silicon substrate having a non-planar silicon body formed therein, the non-planar silicon body having an exposed (111) sidewall;
• a GaN layer disposed on the exposed (111) sidewall of the non-planar silicon body;
• a III-N barrier layer disposed on a (0001) surface of the GaN layer;
• a dielectric layer disposed over the III-N barrier layer;
• a first contact metal disposed on the dielectric layer;
• a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer;
• and
• a third contact disposed on a second n-type semiconductor electrically connected to the 2DEG on a side of the first contact opposite the second contact, wherein the second and third contacts are electrically connected as one voltage node of the capacitor.

A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:

• a (110) silicon substrate having a non-planar silicon body formed therein, the non-planar silicon body having an exposed (111) sidewall;
• a GaN layer disposed on the exposed (111) sidewall of the non-planar silicon body;
• a III-N barrier layer disposed on a (0001) surface of the GaN layer;
• a dielectric layer disposed over the III-N barrier layer;
• a first contact metal disposed on the dielectric layer;
• and
• a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer, wherein the capacitor has a breakdown voltage exceeding 4V across the first and second contacts.