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US 2016/0365291 A1Published application
Vertically integrated memory cell
AssigneeInternational Business Machines Corporation
InventorsJohn E. Barth, JR., Babar A. Khan
Life of this patent
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Abstract
A method of forming a vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor.
Claims20
A method of forming a vertically integrated memory cell comprising:
- forming a deep trench extending into a semiconductor-on-insulator substrate comprising an SOI layer, a buried oxide layer, and a base layer;
- the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer electrically insulates the SOI layer from the base layer;
- forming a trench capacitor located within the deep trench;
- and
- forming a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor, and a gate of the vertical transistor is located within the SOI layer and surrounds the deep trench.
2 more elements
A method of forming a vertically integrated memory cell comprising:
- forming a deep trench extending into a semiconductor-on-insulator substrate comprising an SOI layer, a buried oxide layer, and a base layer;
- the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer electrically insulates the SOI layer from the base layer, the deep trench comprising a sidewall and a bottom;
- forming a trench capacitor located within the deep trench, the trench capacitor comprising a node dielectric disposed along the sidewall and the bottom of the deep trench and an inner electrode disposed on top of the node dielectric;
- and
- forming a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor comprising a channel and a gate, the channel is disposed within the deep trench above and in direct contact with the inner electrode of the trench capacitor, the gate is located within the SOI layer and surrounds the deep trench.
2 more elements
A method of forming a vertically integrated memory cell comprising:
- forming a deep trench extending into a semiconductor-on-insulator substrate, the deep trench comprising a sidewall and a bottom, the semiconductor-on-insulator substrate comprises an SOI layer, a buried oxide layer, and a base layer;
- the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer electrically insulates the SOI layer from the base layer;
- forming a trench capacitor located within the deep trench, the trench capacitor comprising a barrier layer disposed along an entire sidewall and the bottom of the deep trench, a dielectric layer disposed on top of the barrier layer, and an inner electrode disposed on top of the dielectric layer, an upper surface of the inner electrode is below a bottom surface of the SOI layer, and above a top surface of the base layer;
- and
- forming a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor comprising a channel and a gate, the channel is disposed within the deep trench above and in direct contact with the inner electrode of the trench capacitor, the gate is located within the SOI layer and surrounds the channel, and the barrier layer of the trench capacitor separates the gate from the channel.
2 more elements
Dependencies are inferred from the claim text.