Back to results
US 2016/0365147 A1Published application
High speed, high voltage tolerant circuits in flash path
AssigneeCypress Semiconductor Corporation
InventorsBogdan Georgescu, Cristinel Zonte, Vijay Raghavan
Life of this patent
Estimating the term…
Abstract
A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.
Claims20
A circuit comprising:
- a word line coupled to a non-volatile memory (NVM) cell;
- a first path comprising a first inverter and a transistor, the transistor coupled to the word line, the first path coupled to receive a first input voltage signal;
- and
- a second path, wherein at least a portion of the second path is embedded within the first path, wherein the portion of the second path comprises the transistor coupled to the word line, the second path coupled to receive a second input voltage signal, wherein the first input voltage signal is a fast-low-voltage signal that reads the NVM cell, and wherein the second input voltage signal is a slow-high-voltage signal that programs the NVM cell.
1 more element
(canceled)
A non-volatile memory (NVM) device comprising:
- a plurality of cells;
- a global word line driver (GWLDRV);
- a plurality of distributed word line drivers coupled to GWLDRV, the plurality of distributed word line drivers comprising at least a first distributed word line driver coupled to a word line that is coupled to a first cell of the plurality of cells, wherein the first distributed word line driver comprises:
- a first input;
- a second input;
- a first path, coupled to the first input, the first path comprising a first inverter, wherein an output of the first path is coupled to the word line;
- and
- a second path, coupled to the second input, the second path comprising a transistor coupled to the word line, wherein at least a portion of the second path is embedded within the first path,
- wherein the GWLDRV further comprises low-voltage (LV) logic coupled to the first input of the first distributed word line driver and high-voltage (HV) logic coupled to the second input of the first distributed word line driver.
6 more elements
(canceled)
A method comprising:
- receiving, at a first distributed word line driver, a first input signal for a first path and a second input signal for a second path, the first and second input signals to perform an operation on a non-volatile memory (NVM) cell of an NVM device, wherein the first path comprises a first inverter, a second inverter, and a transistor and the second path comprises the second inverter, and wherein a portion of the second path embedded within the first path comprises at least the second inverter;
- propagating, by the first distributed word line driver, the first input signal to the first path;
- propagating, by the first distributed word line driver, the second input signal to the second path, wherein at least a portion of the second path is embedded within the first path;
- outputting, by the first distributed word line driver, to a word line, a first output signal generated in view of the first input signal propagated on the first path;
- and
- outputting, by the first distributed word line driver, to the word line, a second output signal generated in view of the second input signal propagated on the second path.
3 more elements
(canceled)
Dependencies are inferred from the claim text.