Non-Volatile Static RAM and Method of Operation Thereof

A method of operating a memory device including a non-volatile (NV) circuit and a static random access memory (SRAM), the method comprising:

• writing a complementary binary data pair to the SRAM including maintaining a high voltage and a low voltage representing the complementary binary data pair at a first node and a second node of the SRAM, in an SRAM write operation;
• coupling the first and the second nodes to a first and a second ferroelectric capacitors of the NV circuit respectively, wherein each of the first and the second ferroelectric capacitors comprises a first and a second plate electrodes;
• coupling the first plate electrodes of the first and the second ferroelectric capacitors to a common polarization signal;
• coupling the second plate electrodes of the first and second ferroelectric capacitors to drain terminals of first and second discharge transistors of a discharge circuit respectively, wherein source terminals of the first and second discharge transistors are coupled to ground and gates are controlled by a common discharge signal;
• polarizing only one of the first or the second ferroelectric capacitors in a first direction by keeping the common polarization signal at a low level and coupling the high voltage maintained at one of the first node and the second node to the second plate electrode of the one of the first and the second ferroelectric capacitors, in an NV store operation;
• polarizing the one of the first and the second ferroelectric capacitors in a second direction by asserting the common polarization signal to a high level;
• coupling the second plates of the first and the second ferroelectric capacitors to a first and a second bit-lines, respectively;
• and
• reading out the complementary binary data pair stored at the first and the second ferroelectric capacitors to the first bit-line and the second bit-line, respectively, in an NV read operation.

A non-volatile (NV) memory array, comprising:

• a plurality of NV memory cells arranged in rows and columns, each of the plurality of NV memory cells comprising
• a static random access memory (SRAM) circuit including a first data latch node and a second data latch node, wherein the first and the second data latch nodes maintain one bit of binary data and one bit of complementary binary data respectively when operation power is available,
• a ferroelectric random access memory (F-RAM) circuit including a first ferroelectric capacitor (F-Cap) configured to receive and store the one bit of binary data from the first data latch node when the operation power dips below the threshold level, and
• a discharge circuit including first and second discharge transistors controllable by a common discharge signal, wherein drain terminals of the first and second discharge transistors are configured to be coupled to ground and a source terminal of the first discharge transistor is coupled to the first F-Cap to provide a discharge path for charges accumulated thereat, wherein the common discharge signal controls the F-RAM circuits of a same row;
• a plurality of first bit-lines, wherein each of the plurality of first bit-lines is individually coupled to each of the NV circuits of a same column;
• a plurality of second bit-lines, wherein each of the plurality of second bit-lines is individually coupled to each of the NV circuits of the same column;
• and
• wherein the one bit of binary data stored in each of the NV circuits is configured to be output to its corresponding the first bit-line during an NV read operation.