Stacked semiconductor device

A memory device for coupling with a logic integrated circuit (IC) chip having a first input/output (I/O) circuit, the memory device comprising:

• a first memory IC chip having a second I/O circuit formed at a first location on the first memory IC chip;
• a second memory IC chip stacked with the first memory IC chip, the second memory IC chip including a third I/O circuit formed at a second location on the second memory IC chip that corresponds to the first location on the first memory IC chip;
• and
• a link for establishing a point-to-point connection between the first I/O circuit and one of the second I/O circuit or the third I/O circuit.

A memory comprising:

• a logic integrated circuit (IC) chip having a first input/output (I/O) circuit;
• a first memory IC chip stacked with the logic IC chip and having a second I/O circuit formed at a first location on the first memory IC chip;
• a second memory IC chip stacked with the first memory IC chip, the second memory chip including a third I/O circuit formed at a second location on the second memory IC chip that corresponds to the first location on the first memory IC chip;
• and
• a point-to-point link connecting the first I/O circuit to the third I/O circuit.