Display device

A display device, comprising:

• a data driver connected to j- to (j+2)-th data lines;
• a scan driver connected to i- to (i+3)-th scan lines;
• and
• a display panel including k- and (k+1)-th pixel groups, wherein:
• the k-th pixel group includes:
• an i-th transistor having a gate electrode connected to the i-th scan line, a first electrode connected to the j-th data line, and a second electrode connected to an i-th pixel electrode, and
• an (i+1)-th transistor having a gate electrode connected to the (i+1)-th scan line, a first electrode connected to the j-th data line, and a second electrode connected to an (i+1)-th pixel electrode,
• the (k+1)-th pixel group includes:
• an (i+2)-th transistor having a gate electrode connected to the (i+2)-th scan line, a first electrode connected to the (j+1)-th data line, and a second electrode connected to an (i+2)-th pixel electrode, and
• an (i+3)-th transistor having a gate electrode connected to the (i+3)-th scan line, a first electrode connected to the (j+1)-th data line, and a second electrode connected to an (i+3)-th pixel electrode,
• the i- and (i+1)-th transistors are to be turned on at a same time,
• a kickback voltage of the i-th transistor is less than a kickback voltage of the (i+1)-th transistor,
• the (i+2)- and (i+3)-th transistors are to be turned on at the same time, and
• a kickback voltage of the (i+2)-th transistor is less than a kickback voltage of the (i+3)-th transistor.

A display device, comprising:

• first and second scan lines extending on a substrate in a first direction and connected to a scan driver,
• a first data line on the substrate along a second direction intersecting the first direction and insulated from the first and second scan lines;
• a first pixel unit including a first transistor having a gate electrode connected to the first scan line, a first electrode connected to the first data line, and a second electrode connected to a first pixel electrode;
• and
• a second pixel unit including a second transistor having a gate electrode connected to the second scan line, a first electrode connected to the first data line, and a second electrode connected to a second pixel electrode, wherein an overlapping area of the gate electrode and the second electrode of the second transistor is greater than an overlapping area of the gate electrode and the second electrode of the first transistor.