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US 2016/0355393 A1Published application
Chip package and manufacturing method thereof
AssigneeXintec Inc.
InventorsTsang-Yu LIU, Wei-Luen SUEN, Po-Han LEE
Life of this patent
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Abstract
A chip package includes a chip having an upper surface and a lower surface. A sensing element is disposed on the upper surface of the chip, and a thermal dissipation layer is disposed below the lower surface of the chip. A plurality of thermal dissipation external connections are disposed below the thermal dissipation layer and in contact with the thermal dissipation layer.
Claims16
A chip package, comprising:
- a chip having an upper surface and a lower surface;
- a sensing element disposed at the upper surface;
- a thermal dissipation layer disposed at the lower surface;
- and
- a plurality of thermal dissipation external connections disposed underneath and in contact with the thermal dissipation layer.
2 more elements
A method of manufacturing a chip package, the method comprising:
- providing a wafer having an upper surface, a lower surface, and a plurality of chips, wherein each of the chips comprises a sensing element disposed at the upper surface;
- forming a thermal dissipation layer at the lower surface;
- forming an insulating layer covering the thermal dissipation layer;
- removing a portion of the insulating layer to expose the thermal dissipation layer;
- forming a protective layer covering the insulating layer and the thermal dissipation layer;
- removing a portion of the protective layer to expose the thermal dissipation layer;
- and
- forming a plurality of thermal dissipation external connections underneath and in contact with the thermal dissipation layer.
5 more elements
Dependencies are inferred from the claim text.