Length and rate compatible ldpc encoder and decoder

A method of decoding a received digital signal encoded by a linear block code, comprising:

• storing a mother H-matrix defining the linear block code in a memory, the mother H-matrix having a predetermined size;
• receiving a control signal representing at least a payload length of the received digital signal;
• deriving an information shortening set from the control signal;
• modifying the stored mother H-matrix in response to the information shortening set to produce a daughter H-matrix, the daughter H-matrix defining a linear block code smaller than the mother H-matrix;
• storing the daughter H-matrix in the memory of a linear block decoder;
• and
• decoding the received digital signal using the daughter H-matrix stored in the decoder memory.

A method for encoding a digital signal by a linear block code, comprising:

• storing a mother H-matrix defining a linear block code in a memory, the mother H-matrix having a predetermined size;
• receiving a digital signal to be encoded, the digital signal including a data payload;
• receiving a control signal including at least a payload length of the data payload to be encoded;
• deriving an information shortening set from the control signal;
• modifying a mother H-matrix in response to the information shortening set to produce a daughter H-matrix, the daughter H-matrix defining a linear block code smaller than the mother H-matrix;
• storing the daughter H-matrix in the memory of a linear block encoder;
• and
• encoding the received digital signal using the daughter H-matrix stored in the linear block encoder memory.

An apparatus for coding a digital signal, comprising:

• an input for receiving the digital signal;
• an input for receiving a control signal, the control signal including at least a payload length of the digital signal;
• a memory for storing a mother H-matrix defining a linear block code of a predetermined size;
• an allocator connected to receive the control signal and operable to generate an information shortening set;
• a mother H-matrix shortening unit connected to receive the information shortening set and operable to modify the mother H-matrix according to the information shortening set to provide a daughter H-matrix;
• and
• a daughter coding unit connected to receive and store the daughter H-matrix, the daughter coding unit being connected to receive the digital signal and being operable to code the digital signal using the daughter H-matrix stored in the daughter coding unit, the coding being one of encoding or decoding.