Multi-mode discrete-time delta-sigma modulator power optimization using split-integrator scheme

A switched capacitor integrator of a delta-sigma modulator, comprising:

• a first integrator;
• a second integrator, wherein the first integrator and the second integrator are configured to be coupled in parallel to each other;
• at least one switch configured to switch between a first mode and a second mode,
• wherein in the first mode, the first integrator is enabled to operate on at least one input signal to generate an output signal, and
• wherein in the second mode, the first integrator and the second integrator are enabled to cooperatively operate on the at least one input signal, wherein the first integrator generates a first output, the second integrator generates a second output, and the first output converges with the second output to generate the output signal;
• a first delay cell configured to receive the at least one input signal;
• and
• a second delay cell configured to receive the output signal;
• wherein the first integrator is configured to receive at least one of an output of the first delay cell or an output of the second delay cell, and
• wherein the second integrator is configured to receive the at least one of the output of the first delay cell or the output of the second delay cell.

A method for splitting a switched capacitor o of a delta-sigma modulator, comprising:

• coupling a first integrator in parallel to a second integrator;
• switching between a first mode and a second mode;
• enabling the first integrator to operate on at least one input signal to generate an output signal in the first mode;
• disabling the second integrator from operating on the at least one input signal in the first mode;
• and
• enabling the first integrator and the second integrator to cooperatively operate on the at least one input signal in the second mode, wherein in the second mode, the method further comprises:
• generating a first output via the first integrator,
• generating a second output via the second integrator, and
• converging the first output with the second output to generate the output signal.

A method for splitting a switched capacitor integrator of a delta-sigma modulator, comprising:

• coupling a first integrator in parallel to a second integrator;
• switching between a first mode and a second mode;
• enabling the first integrator to operate on at least one input signal to generate an output signal in the first mode;
• enabling the first integrator and the second integrator to cooperatively operate on the at least one input signal in the second mode, wherein in the second mode, the method further comprises:
• generating a first output via the first integrator,
• generating a second output via the second integrator, and
• converging the first output with the second output to generate the output signal;
• receiving, via a first delay cell, the at least one input signal;
• receiving, via a second delay cell, the output signal;
• receiving, via the first integrator, at least one of an output of the first delay cell or an output of the second delay cell;
• and
• receiving, via the second integrator, the at least one of the output of the first delay cell or the output of the second delay cell.

An apparatus for splitting a switched capacitor integrator of a delta-signal modulator, comprising:

• first integrating means;
• second integrating means, wherein the first integrating means and the second integrating means are configured to be coupled in parallel to each other;
• and
• means for switching between a first mode and a second mode,
• wherein in the first mode, the first integrating means is enabled to operate on at least one input signal to generate an output signal and the second integrating means is further configured to be disabled from operating on the at least one input signal, and
• wherein in the second mode, the first integrating means and the second integrating means are enabled to cooperatively operate on the at least one input signal, wherein the first integrating means is configured to generate a first output, the second integrating means is configured to generate a second output, and the first output converges with the second output to generate the output signal.

An apparatus for splitting a switched capacitor integrator of a delta-sigma modulator, comprising:

• first integrating means;
• second integrating means, wherein the first integrating means and the second integrating means are configured to be coupled in parallel to each other;
• means for switching between a first mode and a second mode,
• wherein in the first mode, the first integrating means is enabled to operate on at least one input signal to generate an output signal, and
• wherein in the second mode, the first integrating means and the second integrating means are enabled to cooperatively operate on the at least one input signal, wherein the first integrating means is configured to generate a first output, the second integrating means is configured to generate a second output, and the first output converges with the second output to generate the output signal;
• first delay cell means for receiving the at least one input signal;
• second delay cell means for receiving the output signal,
• wherein the first integrating means is configured to receive an output of the first delay cell means and receive an output of the second delay cell means, and
• wherein the second integrating means is configured to receive the output of the first delay cell means and receive the output of the second delay cell means.

An apparatus for splitting a switched capacitor amplifier, comprising:

• at east two gain stages coupled in parallel to each other wherein the at least two gain stages cooperatively operate on an input signal to generate an output signal by:
• generating, via each stage, a respective output based on the input signal, and
• converging each of the respective outputs to generate the output signal,
• wherein each gain stage comprises:
• an operational transconductance amplifier (OTA);
• a sampling capacitor having a positive terminal coupled to a source of the input signal and a negative terminal coupled to an inverting input of the OTA;
• and
• a feedback capacitor having a positive terminal coupled to an output of the OTA and a negative terminal coupled to the inverting input of the OTA.