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US 2016/0261275 A1Published application
High-reliability holdover method and topologies
AssigneeArbiter Systems, Incorporated
InventorsWilliam J. Dickerson, Robert T. Dickerson
Life of this patent
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Abstract
System and methods for a clock system disciplined to an external reference. In one embodiment, the clock includes a flywheel oscillator controlled by the external reference and a free running holdover oscillator. The holdover oscillator provides increased accuracy during periods of holdover when the external reference is not available. In a further embodiment, the flywheel oscillator is additionally controlled by a phase-locked loop with the holdover oscillator frequency as input, and a control switch for switching the flywheel oscillator to analog control if the phase-locked loop exhibits a fault.
Claims29
A disciplined clock system comprising:
- a flywheel oscillator receiving a tuning voltage and outputting a flywheel oscillator frequency to a first counter responsively outputting a first counter time signal, wherein the flywheel oscillator frequency is controlled by the tuning voltage;
- a holdover oscillator outputting a holdover oscillator frequency to a second counter responsively outputting a second counter time signal;
- a time comparator module communicatively coupled to an external reference, the first counter, and the second counter, the time comparator module configured to perform the steps of:
- receive the first counter time signal, the second counter time signal, and an external reference time signal from the external reference;
- compare the external reference time signal, the first counter time signal and the second counter time signal, wherein a difference between two signals is a time error value;
- and
- responsively output a time error output including at least one time error value;
- a clock control module coupled to the time comparator module and receiving the time error output and performance data from at least one of the holdover oscillator and at least one sensor, and responsively outputting a voltage control;
- and
- a digital-to-analog converter coupled to the clock control module and the flywheel oscillator, the digital-to-analog converter receiving the voltage control and responsively outputting the tuning voltage to the flywheel oscillator;
- wherein the time error output is used by the clock control module to determine the voltage control when the external reference time signal is reliable;
- and
- wherein the time error output and the performance data are used by the clock control module to determine the voltage control when the external reference time signal is unreliable.
10 more elements
A method for operating a disciplined clock system, comprising the steps of:
- determining whether an external reference time signal is available;
- determining, when the external reference time signal is available, whether the external reference time signal is reliable;
- outputting a first counter time signal from a first counter coupled to a flywheel oscillator;
- outputting a second counter time signal from a second counter coupled to a holdover oscillator;
- outputting a time error signal comprising the steps of:
- comparing the external reference time signal, the first counter time signal and the second counter time signal, wherein a difference between two signals is a time error value;
- responsively outputting a time error output including at least one time error value;
- updating a voltage control of the flywheel oscillator by a clock control module, the voltage control based at least on the time error output;
- recording at least one of current holdover oscillator data and sensor data from at least one sensor;
- and
- outputting the first counter time signal from the first counter.
8 more elements
A disciplined clock system comprising:
- a phase-locked loop system comprising:
- a flywheel oscillator controlled by the phased-locked loop system, wherein a flywheel oscillator frequency is output to a first counter;
- a holdover oscillator outputting a holdover oscillator frequency, the holdover oscillator frequency used by the phase-locked loop system to control the flywheel oscillator;
- performance data comprising at least one of holdover oscillator data from the holdover oscillator and sensor data from at least one sensor;
- at least one phase-locked loop parameter used to control the flywheel oscillator;
- the first counter receiving the flywheel oscillator frequency and responsively outputting a first counter time signal;
- a time comparator module communicatively coupled to an external reference and the first counter, the time comparator module configured to perform the steps of:
- receiving the first counter time signal and an external reference time signal from the external reference;
- comparing the external reference time signal and the first counter time signal, wherein a difference between two signals is a time error value;
- and
- responsively outputting a time error output including at least one time error value;
- and
- a clock control module coupled to the time comparator module and configured to receive the performance data, the time error output and responsively output the at least one phase-locked loop parameter to the phase-locked loop system;
- wherein the time error output is used by the clock control module to determine at least one phase-locked loop parameter when the external reference time signal is reliable;
- and
- wherein the performance data are used by the clock control module to determine the at least one phase-locked loop parameter when the external reference time signal is unreliable.
13 more elements
A method for operating a disciplined clock system, comprising the steps of:
- determining whether an external reference time signal is available;
- determining, when the external reference time signal is available, whether the external reference time signal is reliable;
- outputting a first counter time signal from a first counter coupled to a flywheel oscillator;
- outputting a time error output when the external reference time signal is reliable comprising the steps of:
- comparing the external reference time signal and the first counter time signal, wherein a difference between two signals is a time error value;
- and
- responsively outputting a time error output including at least one time error value;
- receiving of the time error output by a clock control module;
- outputting by the clock control module of at least one phase-locked loop parameter to a phase-locked loop including the flywheel oscillator and a holdover oscillator, whereby the flywheel oscillator is controlled at least by the at least one phase-locked loop parameter and the holdover oscillator;
- recording at least one of current holdover oscillator data and sensor data from at least one sensor;
- and
- outputting the first counter time signal from the first counter.
9 more elements
Dependencies are inferred from the claim text.