Damascene process of rram top electrodes

A method of manufacturing a memory, comprising:

• forming an insulating layer over an array of interlayer conductors;
• etching the insulating layer to define a first opening corresponding to a first interlayer conductor in the array, stopping at a first top surface of the first interlayer conductor;
• forming a metal oxide layer on the first top surface of the first interlayer conductor in the first opening;
• depositing a first layer of barrier material conformal with and contacting the metal oxide layer on the first interlayer conductor and surfaces of the first opening, wherein the first opening has a width greater than a width of the first interlayer conductor;
• etching the insulating layer to define a second opening corresponding to a second interlayer conductor in the array, stopping at a second top surface of the second interlayer conductor, subsequent to said depositing the first layer of barrier material;
• depositing a second layer of barrier material conformal with and contacting the first layer of barrier material in the first opening;
• and
• filling the first opening with a conductive material,
• wherein the first and second interlayer conductors are connected to first and second terminals of an access device respectively.