Magnetic memory with tunneling magnetoresistance enhanced spacer layer

Abstract

A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack includes a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a first magnesium layer and a synthetic antiferromagnetic (SAF) layer.

Dependencies are inferred from the claim text.