US 2016/0260843 A1 · ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE AND THIN FILM TRANSISTOR

Abstract

An array substrate and a manufacturing method thereof, a display device and a thin film transistor are provided. The method includes forming a pattern that includes an active layer, a pixel electrode and a data line on a base substrate; forming a pattern that includes a gate insulating layer and at least two gate via-holes therein, the at least two gate via-holes are located in regions in the gate insulating layer that correspond to outer surroundings of the active layer and do not overlap with areas where the pixel electrode and the data line are located; forming a pattern that includes a gate line and at least two gate electrodes, the at least two gate electrodes are connected to the gate line, and are provided in the at least two gate via-holes, respectively. With this method, the fabricating process and the fabricating cost are saved.

Claims20

Dependent claims

A manufacturing method of an array substrate, comprising

forming a pattern that includes an active layer, a pixel electrode and a data line on a base substrate, wherein the active layer and the pixel electrode are located on the same layer and connected to each other, and the data line is located on the active layer;
forming a pattern that includes a gate insulating layer and at least two gate via-holes in the gate insulating layer on the pattern of the active layer, the pixel electrode and the data line, wherein the gate via-holes are located in regions in the gate insulating layer that correspond to outer surroundings of the active layer and do not overlap with areas where the pixel electrode and the data line are located, the gate via-holes are separated from the active layer, the pixel electrode and the data line by the gate insulating layer;
and
forming a pattern that includes at least one gate line and at least two gate electrodes, wherein the at least two gate electrodes are connected to the at least one gate line, and are provided in the at least two gate via-holes, respectively.

1 more element

A thin film transistor, comprising a source electrode, an active layer, a drain electrode, a gate insulating layer and at least two gate electrodes,

wherein the source electrode and the active layer at least partially overlap, the drain electrode and the active layer are located on a same layer and connected together, the gate insulating layer covers the source electrode, the active layer and the drain electrode, in regions in the gate insulating layer that correspond to outer surroundings of the active layer and do not overlap with areas where the drain electrode and the source electrode are located, there are formed at least two gate via-holes, and the at least two gate via-holes are separated from the active layer, the pixel electrode and the data line by the gate insulating layer;
the at least two gate electrodes are connected to at least one gate line, and provided in the at least two gate via-holes, respectively.

Dependencies are inferred from the claim text.

Array substrate and manufacturing method thereof, display device and thin film transistor

Life of this patent

Array substrate and manufacturing method thereof, display device and thin film transistor

Life of this patent

Abstract

Claims20