Etsoi with reduced extension resistance

A semiconductor device comprising:

• a silicon substrate;
• a buried oxide (BOX) layer on the silicon substrate;
• a thin silicon layer on the BOX layer, the thin silicon layer having a thickness of about 6 nm to about 8 nm;
• a high-k metal gate electrode formed on the thin silicon layer;
• an epitaxially formed silicon-containing layer on the thin silicon layer, surrounding at least a bottom portion of the high-k metal gate electrode.

A semiconductor device comprising:

• a silicon substrate;
• a buried oxide (BOX) layer on the silicon substrate;
• a silicon layer having a thickness of about 6 nm to about 8 nm on the BOX layer;
• a high-k metal gate electrode formed on the silicon layer;
• an epitaxially formed silicon germanium layer on the silicon layer, surrounding at least a bottom portion of the high-k metal gate electrode;
• a first spacer on the silicon germanium layer on each side of the high-k metal gate electrode;
• a second spacer on each first spacer;
• and
• a raised faceted source/drain region on the silicon germanium layer, adjacent each first spacer.