Heterojunction tunnel field effect transistor fabrication using limited lithography steps

A method of forming a heterojunction tunnel field effect transistor (TFET) comprising:

• forming a gate stack on a substrate;
• forming first-type source/drain regions in the substrate on either side of the gate stack;
• forming an interlevel dielectric (ILD) layer on the gate stack and the first-type source/drain regions;
• forming a first opening in the ILD layer to expose an upper surface of one of the first-type source/drain regions;
• removing the exposed first-type source-drain region to form a recess;
• forming a second-type source/drain region in the recess, the second-type source/drain region having an opposite conductivity type as the first-type source/drain regions;
• forming a first contact liner on the second-type source/drain region, the gate stack, and a vertical sidewall of the ILD layer;
• and
• forming a first contact on the first contact liner.

A heterojunction tunnel field effect transistor (TFET) structure comprising:

• a first-type source/drain region in a substrate adjacent to a first side of a gate stack;
• a second-type source/drain region in the substrate adjacent to a second side of the gate stack, wherein the second-type source/drain region has an opposite conductivity type as that of the first-type source/drain region, and wherein the second-type source/drain region has an undercut region that extends below a portion of the gate stack;
• an interlevel dielectric (ILD) layer on the gate stack;
• a first contact on the second-type source/drain region and the gate stack;
• and
• a second contact on the first-type source/drain region.