Connections for memory electrode lines
AssigneeMicron Technology, Inc.
InventorHernan A. Castro
Life of this patent
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AssigneeMicron Technology, Inc.
InventorHernan A. Castro
Estimating the term…
Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.
An integrated circuit having a plurality of conductive lines formed at a first vertical level and extending in a first lateral direction and connected to interconnect structures formed at a second vertical level different from the first vertical level, the conductive lines comprising:
An integrated circuit device, comprising:
A memory device, comprising:
A memory array, comprising:
Dependencies are inferred from the claim text.