Memory cell structure, method of manufacturing a memory, and memory apparatus

A method of manufacturing a memory having a memory cell structure including a transistor and a memory element, the transistor using a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions, the memory element being disposed below the first diffusion layer, the first diffusion layer being electrically connected to the memory element via a contact formed after the silicon substrate is thinned,

• the method comprising the step of forming an intermediate laminated body as a part of the memory cell structure by performing at least the steps of:
• forming field isolation layers at a predetermined depth of the silicon substrate;
• forming the groove-shaped concave portion between the field isolation layers;
• forming the first diffusion layer in the bottom portion of the concave portion;
• forming the second diffusion layer in the upper end portions of the sidewall portions of the concave portion;
• and
• forming a metal wire in an upper portion of the second diffusion layer.

A memory apparatus, comprising:

• a memory cell including a memory element that holds information depending on a magnetization state of a magnetic body;
• and
• two types of wires mutually intersect and other types of wires,
• the memory cell having a memory cell structure including
• a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions, and
• the memory element that is disposed below the first diffusion layer, the first diffusion layer being electrically connected to the memory element via a contact formed after the silicon substrate is thinned,
• the memory element being provided to a current between the two types of wires via the transistor.