Thin film transistor and method of manufacturing the same, array substrate and display apparatus

Abstract

The present disclosure discloses a thin film transistor comprising: an active layer; an etching barrier layer arranged on the active layer and formed with a plurality of via holes therein; and a source electrode and a drain electrode arranged on the etching barrier layer, wherein the source electrode comprises at least two sub source electrodes and the drain electrode comprises at least two sub drain electrodes; and the sub source electrodes and the sub drain electrodes constitute at least two parallel sub-switches, each of which comprises a sub source electrode and a sub drain electrode, and the sub source electrode and the sub drain electrode are electrically connected to the active layer through the via holes in the etching barrier layer, respectively. The present disclosure further discloses a method of manufacturing a thin film transistor, an array substrate and a display apparatus. The present disclosure employs a multi-channel design with which the DGS problem due to an incomplete active layer is solved by using a plurality of parallel sub-switches, ensuring the normal operation of the pixel and thus increasing yield and useful life of product.

Dependencies are inferred from the claim text.