Manufacture method of tft substrate and sturcture thereof

An oxide semiconductor TFT substrate structure, comprising a substrate, a gate on the substrate, a first heavily doped transparent conducting thin film layer at a lower surface of the gate with the same shape of the gate, a gate isolation layer on the gate and the substrate, an island shaped oxide semiconductor layer directly over the gate on the gate isolation layer, an island shaped etching stopper layer on the island shaped oxide semiconductor layer, a source/a drain on the island shaped etching stopper layer and the gate isolation layer, a third heavily doped transparent conducting thin film layer at a lower surface of the source/the drain with the same shape of the source/the drain, a third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain, a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer and a pixel electrode layer on the protecting layer;

• the island shaped oxide semiconductor layer comprises a central part and two side parts;
• a width of the island shaped etching stopper layer is smaller than a width of the oxide semiconductor layer and only a central part is covered;
• the source/the drain contact the two side parts via the second heavily doped transparent conducting thin film layer to establish electrical connections;
• the protecting layer comprises a via located at one side of the island shaped oxide semiconductor layer, and the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections.

An oxide semiconductor TFT substrate structure, comprising a substrate, a gate on the substrate, a first heavily doped transparent conducting thin film layer at a lower surface of the gate with the same shape of the gate, a gate isolation layer on the gate and the substrate, an island shaped oxide semiconductor layer directly over the gate on the gate isolation layer, an island shaped etching stopper layer on the island shaped oxide semiconductor layer, a source/a drain on the island shaped etching stopper layer and the gate isolation layer, a third heavily doped transparent conducting thin film layer at a lower surface of the source/the drain with the same shape of the source/the drain, a third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain, a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer and a pixel electrode layer on the protecting layer;

• the island shaped oxide semiconductor layer comprises a central part and two side parts;
• a width of the island shaped etching stopper layer is smaller than a width of the oxide semiconductor layer and only a central part is covered;
• the source/the drain contact the two side parts via the second heavily doped transparent conducting thin film layer to establish electrical connections;
• the protecting layer comprises a via located at one side of the island shaped oxide semiconductor layer, and the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections;
• wherein material of the source/the drain is copper, material of the first heavily doped transparent conducting thin film layer, and the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer is heavily doped ITO or heavily doped IZO;
• the island shaped oxide semiconductor layer is an IGZO semiconductor layer, and material of the protecting layer is SiO2 or SiON, and material of the pixel electrode layer is ITO or IZO;
• thicknesses of the first heavily doped transparent conducting thin film layer, the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer are respectively in a range of 5-200 nm.