Semiconductor device, semiconductor memory device, and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, comprising:

• dividing a semiconductor region into a plurality of active areas by an element isolation insulating film;
• forming a gate electrode material above the active area and the element isolation insulating film;
• etching the element isolation insulating film and the gate electrode material above the element isolation insulating film to form a first element isolation trench;
• and
• further implanting an element isolation insulating film in the first element isolation trench.

A semiconductor memory device, comprising:

• a memory cell active area where a memory cell is provided;
• a peripheral transistor active area where a peripheral transistor is formed, the peripheral transistor configuring a peripheral circuit that controls the memory cell;
• an element isolation insulating film that insulates and isolates the memory cell active area and the peripheral transistor active area;
• a memory insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode sequentially disposed on an surface of the memory cell active area;
• and
• a gate electrode disposed sandwiching a gate insulating film, on the peripheral transistor active area,
• the element isolation insulating film that insulates and isolates the peripheral transistor active area comprising:
• a first element isolation insulating film having a first width;
• and a second element isolation insulating film having a second width larger than the first width,
• the first element isolation insulating film including in an surface thereof a first element isolation trench having a third width,
• the second element isolation insulating film including in an surface thereof a second element isolation trench having a fourth width larger than the third width,
• the first element isolation trench having disposed therein a third element isolation insulating film,
• the second element isolation trench having disposed therein a fourth element isolation insulating film different from the third element isolation insulating film, and
• a height of an surface of the element isolation insulating film that insulates and isolates the memory cell active area being higher than a height of an surface of the floating gate electrode.