Nonvolatile memory cell structure with assistant gate and memory array thereof

A non-volatile memory (NVM) array, comprising:

• a plurality of NVM cells, wherein each of the NVM cells comprises:
• a semiconductor substrate having therein a first N well;
• a first oxide define (OD) region and a second oxide define (OD) region disposed within the semiconductor substrate;
• a PMOS select transistor disposed on the first OD region, wherein the PMOS select transistor comprises a select gate, a first P+ source doping region in the first N well, and a second P+ doping region spaced apart from the first P+ source doping region;
• a PMOS floating gate transistor serially connected to the PMOS select transistor and being disposed over the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region, the second P+ doping region, and a third P+ doping region spaced apart from the second P+ source doping region, wherein the PMOS floating gate transistor serves as a charge storage element of the NVM cell;
• an assistant gate protruding from the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region, wherein the assistant gate is formed integrally with the floating gate using a single layer of polysilicon;
• a plurality of word lines extending along a first direction, wherein each of the word lines is electrically connected to the select gate of the PMOS select transistor of each of the plurality of NVM cells;
• a plurality of bit lines extending along a second direction, wherein each of the bit lines is electrically connected to the third P+ doping region of the PMOS floating gate transistor of each of the plurality of NVM cells;
• and
• a plurality of source lines, wherein each of the source lines is electrically connected to the first P+ doping region of the PMOS select transistor of each of the plurality of NVM cells.