Semiconductor device and manufacturing method of semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorTakashi OHASHI
Life of this patent
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Abstract
According to one embodiment, a semiconductor device includes a pair of selection gate transistors arranged on a semiconductor layer, and memory cell transistors arranged on the semiconductor layer between the pair of selection gate transistors. The memory cell transistors are connected to each other in series such that every two adjacent ones of the memory cell transistors share a source/drain region. Further, the memory cell transistors are arranged in an odd number between the pair of selection gate transistors.
Claims19
A semiconductor device comprising:
- a pair of selection gate transistors arranged on a semiconductor layer;
- and
- memory cell transistors arranged on the semiconductor layer between the pair of selection gate transistors, the memory cell transistors being connected to each other in series such that every two adjacent ones of the memory cell transistors share a source/drain region,
- wherein the memory cell transistors are arranged in an odd number between the pair of selection gate transistors.
A manufacturing method of a semiconductor device, the method comprising:
- forming a first mask layer above a processing object film;
- forming a first resist pattern having a first size on the first mask layer in a memory cell region by use of a lithography technique;
- forming a first sidewall film having a first thickness on the first mask layer;
- etching back the first sidewall film;
- removing the first resist pattern;
- forming a second resist pattern having a second size larger than the first size on the first mask layer in the memory cell region and a peripheral circuit region by use of a lithography technique;
- forming a second sidewall film having a second thickness on the first mask layer;
- etching back the second sidewall film;
- removing the second resist pattern;
- etching the first mask layer through the second sidewall film serving as a mask;
- and
- etching the processing object film.
A manufacturing method of a semiconductor device, the method comprising:
- forming a second processing object film and a first mask layer on a first processing object film;
- forming a first resist pattern having a first size on the first mask layer in a memory cell region by use of a lithography technique;
- forming a first sidewall film having a first thickness on the first mask layer;
- etching back the first sidewall film;
- removing the first resist pattern;
- forming a second resist pattern having a second size larger than the first size on the first mask layer in the memory cell region and a peripheral circuit region by use of a lithography technique;
- forming a second sidewall film having a second thickness on the first mask layer;
- etching back the second sidewall film;
- removing the second resist pattern;
- etching the first mask layer through the second sidewall film serving as a mask;
- etching the second processing object film through the first mask layer serving as a mask;
- forming a second mask layer on the first processing object film including the second processing object film thus processed;
- forming a third resist pattern having a third size on the second mask layer in the peripheral circuit region by use of a lithography technique;
- etching the second mask layer through the third resist pattern serving as a mask;
- and
- etching the first processing object film through the second mask layer and the second processing object film, which serve as a mask,
- wherein the forming a third resist pattern includes positioning the third resist pattern to have its end arranged above a portion of the second sidewall film formed adjacent to the first sidewall film.
Dependencies are inferred from the claim text.