US 2016/0260720 A1 · SRAM MEMORY CELL AND SRAM MEMORY

Abstract

Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.

Claims21

Dependent claims

-10. (canceled)

An SRAM memory cell comprising:

a first PMOS transistor;
a second PMOS transistor;
a first NMOS transistor;
a second NMOS transistor;
a third NMOS transistor;
and a fourth NMOS transistor, wherein:
a first insulating layer is disposed on a first portion of a top surface of a gate electrode layer of the first PMOS transistor to expose a second portion of the top surface of the gate electrode layer of the first PMOS transistor adjacent to a drain of the second PMOS transistor, such that a first opening is formed and surrounded by the first insulating layer, the exposed second portion of the gate electrode layer, the drain of the second PMOS transistor, and a gate of the second PMOS transistor;
and
a first conductive layer at least partially covers a bottom and a sidewall of the first opening for electrically connecting the gate of the first PMOS transistor with the drain of the second PMOS transistor.

6 more elements

An SRAM memory comprising:

at least one SRAM memory cell, each SRAM memory cell comprising:
a first PMOS transistor;
a second PMOS transistor;
a first NMOS transistor;
a second NMOS transistor;
a third NMOS transistor;
and a fourth NMOS transistor, wherein:
a first insulating layer is disposed on a first portion of a top surface of a gate electrode layer of the first PMOS transistor to expose a second portion of the top surface of the gate electrode layer of the first PMOS transistor adjacent to a drain of the second PMOS transistor, such that a first opening is formed and surrounded by the first insulating layer, the exposed second portion of the gate electrode layer, the drain of the second PMOS transistor, and a gate of the second PMOS transistor;
and
a first conductive layer at least partially covers a bottom and a sidewall of the first opening for electrically connecting the gate of the first PMOS transistor with the drain of the second PMOS transistor.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/153,318Filed 12 May 2016

Priority

CN 2012-10393117.116 Oct 2012

Published

8 Sep 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10B 10/00
Static random access memory [sram] devices
H10D 84/0149
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Sram memory cell and sram memory

Life of this patent

Sram memory cell and sram memory

Life of this patent

Abstract

Claims21