Esd snapback based clamp for finfet

A method for fabricating a field effect transistor for use as an ESD protection device, the method comprising:

• patterning a gate and a spaced apart dummy gate on a substrate;
• forming a source diffusion region in the substrate;
• forming a first drain diffusion region in the substrate between the gate and the dummy gate,
• forming a second drain diffusion region in the substrate spaced apart from the first diffusion region and having a section spaced farther from the gate than the dummy gate;
• doping the substrate to form a doped region that merges the first drain diffusion region and the second drain diffusion region and to form a non-doped region that extends between the source diffusion region and the first drain diffusion region below the gate;
• and
• forming a contact on a drain having the second drain diffusion region.