Separated lower select line in 3d nand architecture

A memory device on a substrate, comprising:

• a multilevel stack of conductive layers, each of the layers being divided laterally into a set of at least one word line;
• a plurality of pillars oriented orthogonally to the conductive layers, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the conductive layers;
• a plurality of string select lines disposed above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective string select gate of the pillar, a number NSSL of the string select lines superposing a first one of the word lines;
• a plurality of parallel bit line conductors disposed above the string select lines, each of the bit line conductors superposing a respective distinct subset of the pillars, each of the pillars underlying one of the bit line conductors;
• and
• a plurality of ground select lines disposed below the conductive layers, each of the ground select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a ground select line defining a respective ground select gate of the pillar, a number NGSL of the ground select lines underlying the first word line,
• wherein the number NGSL of the ground select lines underlying the first word line is between 1 and the number NSSL of the string select lines superposing the first word line, exclusive.

A memory device on a substrate, comprising:

• a multilevel stack of conductive layers, each of the layers being divided laterally into a set of at NWL≧1 word lines spaced from each other in a bit line direction, the set of word lines defining an array width in the bit line direction;
• a plurality of pillars oriented orthogonally to the conductive layers, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the conductive layers;
• NSSL string select lines disposed above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective string select gate of the pillar, the string select lines being spaced from each other in the bit line direction and collectively covering the array width;
• a plurality of parallel bit line conductors disposed above the string select lines and defining the bit line direction, each of the bit line conductors superposing a respective distinct subset of the pillars, each of the pillars underlying one of the bit line conductors;
• and
• NGSL ground select lines disposed below the conductive layers, each of the ground select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a ground select line defining a respective ground select gate of the pillar, the ground select lines being spaced from each other in the bit line direction and collectively covering the array width,
• wherein the number NGSL of the ground select lines covering the array width is different from both the number of string select lines NSSL covering the array width and the number of word lines NWL covering the array width.

A memory device comprising:

• a plurality NP of strings of series-connected memory cells, each of the strings having an equal number NC>1 of the memory cells, each of the strings further having a string select gate and a ground select gate series-connected at opposite ends of the string, each of the memory cells and each of the string select gates and each of the ground select gates having a respective control gate electrode;
• a first plurality of separate word line conductors, each i'th one of the word line conductors being connected to the control gate electrode of a corresponding i'th one of the memory cells in all of the strings in the plurality of strings;
• a plurality of NSSL of separate string select line conductors, each j'th one of the string select line conductors being connected to all the control gate electrodes of all the string select gates in a corresponding j'th distinct non-null subset of the string select gates;
• and
• a plurality NGSL of separate ground select line conductors, each k'th one of the ground select line conductors being connected to the control gate electrode of all the ground select gates in a corresponding k'th distinct non-null subset of the ground select gates,
• wherein the number NSSL of string select line conductors in the plurality of string select line conductors is different from the number NGSL of ground select line conductors in the plurality of ground select line conductors.