Memory self-testing device and method thereof

A memory self-testing method, for testing a plurality of memory control units, comprising:

• generating a plurality of access request signals to the memory control units;
• determining a leading feedback signal among a plurality of feedback signals, the feedback signals being generated by the memory control units in response to the access request signals;
• generating a plurality of sets of data according to the leading feedback signal, and temporarily storing the sets of data;
• and
• transmitting the sets of data to the memory control units according a plurality of read/write signals, the read/write signals being generated by the memory control units in response to the access request signals.

A circuit system, comprising:

• a plurality of memory control units, controlling a plurality of memory components;
• a function module, coupled to the memory control units, accessing the memory components through the memory control units;
• and
• a memory self-testing device, coupled to the memory control units, simultaneously testing the memory control units.