Semiconductor device, pre-write program, and restoration program

A semiconductor device comprising:

• a memory array including a plurality of twin cells each formed of electrically rewritable, first and second storage devices holding binary data depending on a difference between a threshold voltage of said first storage device and a threshold voltage of said second storage device;
• and
• a control circuit that controls an erase process allowing said plurality of twin cells in a state with data written therein to be placed in an erased state in response to an erase command,
• said control circuit performing said erase process to allow said plurality of twin cells to have at least some thereof with one or two or more memory cells placed in an erased state that inverts in magnitude a relationship in threshold value that said first and second storage devices have with the data written therein.

A semiconductor device comprising:

• a memory array including a plurality of twin cells each formed of electrically rewritable, first and second storage devices holding binary data depending on a difference between a threshold voltage of said first storage device and a threshold voltage of said second storage device;
• and
• a control circuit that controls an erase process allowing said plurality of twin cells in a state with data written therein to be placed in a first erased state in response to a first erase command and a second erased state in response to a second erase command,
• when said plurality of twin cells in the state with the data written therein are placed in said second erased state, said plurality of twin cells having a larger number thereof with said first and second storage devices having threshold values, respectively, in a relationship inverted in magnitude than when said plurality of twin cells in the state with the data written therein are placed in said first erased state.