Semiconductor Device

A semiconductor device comprising:

• a non-volatile memory unit;
• and
• a control circuit configured to assign a physical address to an input logical address and to access the physical address of the non-volatile memory unit, wherein
• the non-volatile memory unit includes a plurality of word lines, a plurality of bit lines that intersects with the plurality of word lines, and a plurality of memory cell groups arranged in intersection points of the plurality of word lines and the plurality of bit lines,
• each of the plurality of memory cell groups includes first to Nth memory cells connected to each other in series, and first to Nth memory-cell selection lines that respectively select the first to Nth memory cells,
• each of the first to Nth memory cells includes a selection transistor including a gate electrode connected to one of the first to Nth memory-cell selection lines, and a resistive storage element connected to the selection transistor in parallel, and
• the control circuit sets, as a first area, a plurality of memory cell groups arranged in a manner adjacent to each other, simultaneously writes a first logical level into N of the first to Nth memory cells in each of the plurality of memory cell groups in the first area, sets, as a second area, a memory cell group arranged in an adjacent manner in an outer periphery of the first area, and does not write the first logical level into the memory cell group in the second area.

A semiconductor device comprising:

• a non-volatile memory unit;
• and
• a control circuit configured to assign a physical address to an input logical address and to access the physical address of the non-volatile memory unit,
• wherein the non-volatile memory unit includes a plurality of first signal lines, a plurality of second signal lines that intersects with the plurality of first signal lines, and a plurality of memory cell groups arranged in intersection points of the plurality of first signal lines and the plurality of second signal lines,
• each of the plurality of memory cell groups includes first to Nth (N is integer number equal to or larger than 2) memory cells, and first to Nth memory-cell selection lines that respectively select the first to Nth memory cells, and
• the control circuit sets, as a first area, a plurality of memory cell groups arranged in a manner adjacent to each other, sets, as a second area, a memory cell group arranged in an adjacent manner in an outer periphery of the first area, and simultaneously writes a first logical level into N of the first to Nth memory cells in each of the plurality of memory cell groups in the first area and the second area.