Semiconductor memory device and method of manufacturing the same

A semiconductor memory device, comprising:

• a memory cell array;
• and
• a control circuit that controls a voltage applied to the memory cell array,
• the memory cell array comprising:
• a first wiring line extending in a first direction;
• a second wiring line extending in a second direction, the second direction intersecting the first direction;
• a memory cell disposed at an intersection of the first wiring line and the second wiring line, the memory cell including a variable resistance layer;
• a third wiring line extending in a third direction, the third direction intersecting the first direction and the second direction;
• and
• a select transistor connected between the first wiring line and the third wiring line, the select transistor switching electrical connection/non-connection of the first wiring line and the third wiring line,
• the variable resistance layer being formed by a hafnium oxide crystalline film in which a proportion of a component oriented in a (−1, 1, 1) plane and a (1, 1, 1) plane is 90% or more.

A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising:

• a memory cell array;
• and a control circuit that controls a voltage applied to the memory cell array, the memory cell array comprising:
• a first wiring line;
• a second wiring line intersecting the first wiring line;
• and a memory cell disposed at an intersection of the first and second wiring lines, the memory cell including a variable resistance element, the variable resistance element being formed by a hafnium oxide crystalline film in which a proportion of a component oriented in a (−1, 1, 1) plane and a (1, 1, 1) plane is 90% or more, the method comprising:
• the hafnium oxide crystalline film being manufactured by a film-forming process by atomic layer deposition, employing an inorganic type hafnium precursor.

A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising:

• a memory cell array;
• and a control circuit that controls a voltage applied to the memory cell array, the memory cell array comprising:
• a first wiring line extending in a first direction;
• a second wiring line extending in a second direction, the second direction intersecting the first direction;
• a memory cell disposed at an intersection of the first wiring line and the second wiring line, the memory cell including a variable resistance layer;
• a third wiring line extending in a third direction, the third direction intersecting the first direction and the second direction;
• and a select transistor connected between the first wiring line and the third wiring line, the select transistor switching electrical connection/non-connection of the first wiring line and the third wiring line, the variable resistance layer being formed by a hafnium oxide crystalline film in which a proportion of a component oriented in a (−1, 1, 1) plane and a (1, 1, 1) plane is 90% or more, the method comprising:
• the hafnium oxide crystalline film being manufactured by a film-forming process by atomic layer deposition, employing an inorganic type hafnium precursor.